Memory device and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJung-Piao Chiu, Yu-Sheng Chen
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Abstract
A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.
Claims20
A memory device, comprising:
- a memory cell array comprising:
- first-tier word lines extending in a first direction;
- second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction;
- and
- bit lines extending in a third direction angularly offset from the first and second directions, and the bit lines being arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.
A memory device, comprising:
- a memory cell array comprising:
- first word line branches connected together through a first common connection and disposed on a first level of the memory cell array, the first word line branches extending in a first direction, and the first common connection extending in a second direction different from the first direction;
- second word line branches connected together through a second common connection and disposed on a second level of the memory cell array, the second word line branches extending in the second direction, and the second common connection extending in the first direction;
- bit lines extending in a third direction different from the first and second directions and passing through the first and second levels of the memory cell array.
A memory device, comprising:
- a memory cell array comprising:
- first word lines disposed on a first level of the memory cell array;
- second word lines disposed on a second level of the memory cell array, each of the second word lines comprising overlapping regions interleaved with non-overlapping regions, wherein each of the overlapping regions overlaps one of the first word lines;
- and
- bit lines extending through the first and second levels of the memory cell array, and the bit lines adjoining the non-overlapping region, wherein the first and second levels are stacked upon one another in a height direction of the bit lines.
Dependencies are inferred from the claim text.