Semiconductor wiring device and method
AssigneeMicron Technology, Inc.
InventorsHidenori Yamaguchi, Keizo Kawakita
Life of this patent
Estimating the term…
Abstract
Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a first transmission line and a second transmission line located over one another. A via is shown connecting the first transmission line and a second transmission line wherein a first side of the via and a side of the second transmission line are coplanar. A via is also shown connecting the first transmission line and a second transmission line wherein the second transmission line tapers downward from a line width to a via width.
Claims17
A semiconductor device, comprising:
- a first transmission line on a semiconductor substrate;
- a second transmission line in a layer above the first transmission line, the second transmission line having a line width;
- and
- a via coupled between the first transmission line and the second transmission line, wherein the via has a via width smaller than the line width;
- wherein the second transmission line tapers downward from the line width to the via width.
A semiconductor device, comprising:
- a first transmission line on a semiconductor substrate;
- a second transmission line in a layer above the first transmission line, the second transmission line having a line width;
- and
- a via coupled between the first transmission line and the second transmission line;
- wherein a first side of the via and a side of the second transmission line are coplanar.
A method, comprising:
- forming a first transmission line on a semiconductor substrate;
- forming a dielectric over the first transmission line;
- using a trench mask to lithographically form a trench in the dielectric for a second transmission line above the first transmission line;
- using a via mask to lithographically form a via opening in the dielectric, wherein a via mask footprint and a trench mask footprint overlap in an intersection region smaller than either the via mask or the trench mask, and wherein the via opening is dimensioned by the intersection region;
- and
- filling the trench and via opening in a single conductor deposition operation.
Dependencies are inferred from the claim text.