Memory testing system and memory testing method
AssigneeNanya Technology Corporation
InventorChien Yu Chen
Life of this patent
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Abstract
The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.
Claims18
A memory testing system, comprising:
- at least one memory device;
- a power supply configured to provide a first reference voltage to the at least one memory device according to a control signal;
- and
- a processor configured to:
- provide the control signal to control the power supply to vary the first reference voltage among a plurality of voltage levels;
- and
- test the at least one memory device under the plurality of voltage levels to generate a plurality of first testing results corresponding to the plurality of voltage levels,
- wherein the processor is further configured to execute a first testing program and control the power supply to vary the first reference voltage from a first voltage level of the plurality of voltage levels to a second voltage level of the plurality of voltage levels to generate the plurality of first testing results corresponding to the first testing program, and
- execute a second testing program different from the first testing program and control the power supply to vary the first reference voltage from the first voltage level to the second voltage level to generate a plurality of second testing results corresponding to the second testing program,
- wherein the first voltage level is one of a lowest one of the plurality of voltage levels and a highest one of the plurality of voltage levels, and
- the second voltage level is another one of the lowest one of the plurality of voltage levels and the highest one of the plurality of voltage levels.
A memory testing method, comprising:
- providing a first reference voltage to a first memory device;
- adjusting the first reference voltage from a first voltage level to a second voltage level during a plurality of time periods;
- and
- testing the first memory device during the plurality of time periods in response to each of the first voltage level and the second voltage level,
- providing a second reference voltage to a second memory device different from the first memory device;
- adjusting the second reference voltage from one of the first voltage level and the second voltage level to another one of the first voltage level and the second voltage level during the plurality of time periods;
- and
- applying a testing signal to test the second memory device during the plurality of time periods in response to the second reference voltage,
- wherein testing the first memory device comprises applying the testing signal to the first memory device.
Dependencies are inferred from the claim text.