Programmable logic device with design for test functionality

An integrated circuit comprising:

• a programmable logic device (PLD), wherein the PLD comprises:
• a scan enable input, wherein, when the scan enable input is asserted, the PLD enters a shift mode;
• and
• at least one first logic block section, wherein the first logic block section includes:
• a first configurable memory bit coupled to a scan chain in the shift mode;
• a first multiplexer (MUX) with a first select input directly coupled to the first configurable memory bit;
• and
• a first configurable look up table (LUT) including a first plurality of configurable memory bits coupled in series along the scan chain in the shift mode and coupled in series to the first configurable memory bit, a second MUX with a select input directly coupled to the first MUX, and a third plurality of MUXes, the third plurality of MUXes each including:
• a first input coupled to one of the first plurality of configuration memory bits;
• and
• a second input coupled to a different one of the first plurality of configuration memory bits than the first input of the third plurality of MUXes.

A method, comprising:

• operating a programmable logic device (PLD) in a shift mode, the PLD including a scan enable input, and at least one logic block section, wherein the at least one logic block section includes:
• a first configurable memory bit coupled to a scan chain in the shift mode and including a first register and a first scannable register multiplexer (MUX);
• a first MUX with a first select input coupled to the first of configurable memory bit;
• and
• a first configurable look up table (LUT) including:
• a first plurality of configurable memory bits coupled in series along the scan change in the shift mode, each configurable memory bit of the first plurality of configurable memory bits including a second register and a second scannable register MUX;
• and
• a plurality of MUXes coupled to each of the first plurality of configurable memory bits and to the first MUX;
• a second MUX coupled to the first MUX, coupled to the first configurable LUT;
• activating the shift mode in the PLD by asserting the scan enable input;
• storing data from the scan in input into the first configurable memory bit;
• activating a scan capture mode in the PLD by de-asserting the scan enable input.