Non-volatile memory device and programming method thereof

An operating method of a non-volatile memory device comprising a plurality of cell strings connected to a plurality of bit lines, wherein the plurality of cell strings comprise a plurality of string select transistors respectively connected to the plurality of bit lines, the operating method comprising:

• applying a first voltage comprising a first level to a first bit line and a second bit line from among the plurality of bit lines during a first time period, wherein the first bit line and the second bit line are respectively connected to a first cell string and a second cell string from among the plurality of cell strings;
• applying a second voltage comprising a second level to the first bit line during a second time period subsequent to the first time period;
• turning on first string select transistors, from among the plurality of string select transistors, included in a cell string connected to the first bit line during the second time period;
• turning off second string select transistors, from among the plurality of string select transistors, included in a cell string connected to the second bit line during the second time period;
• and
• maintaining a third voltage applied to the second bit line at the first level during the second time period by electrically disconnecting a channel of a second select stack included in the second cell string and the second bit line from each other by applying a first dummy voltage to at least one second transistor adjacent to a boundary between a stack adjacent to the second select stack and the second select stack.

A non-volatile memory device comprising:

• a memory cell array comprising a plurality of cell strings;
• a voltage generator configured to generate a voltage applied to a bit line connected to the plurality of cell strings;
• and
• a control circuit configured to program data received from the outside to the memory cell array,
• wherein the control circuit is further configured to:
• control an electrical connection between a select stack comprising a select word line and a stack adjacent to the select stack by:
• controlling at least one transistor adjacent to a boundary between the select stack and the stack adjacent to the select stack, and
• controlling a voltage applied to a non-select word line connected to the stack adjacent to the select stack to maintain a first level during a time period in which a plurality of program loops for the memory cell array are performed, such that the voltage applied to the non-select word line connected to the stack adjacent to the select stack is maintained at the first level over multiple bit line setup periods and multiple program execution periods of the plurality of program loops.