Nonvolatile memory device including combined sensing node and cache read method thereof

A nonvolatile memory device comprising:

• a cell array comprising a plurality of memory cells serially coupled to bit lines;
• a page buffer circuit including a plurality of page buffer units configured to program or sense at least one of the plurality of memory cells through the bit lines and electrically connect or block adjacent sensing node lines in response to a pass control signal;
• and
• a control circuit configured to
• suspend a program operation, and
• while the program operation is suspended, move first data corresponding to a first state sensed through a first sensing node line in a first sensing latch of a first page buffer unit to a second sensing node line of a second page buffer unit during a cache read operation, and to control the page buffer circuit such that the first sensing latch performs an on-chip valley search (OVS) for reading a second state of the first sensing node line,
• wherein, while the program operation is suspended, the plurality of page buffer units are occupied by write data of the program operation.

A cache read method of a nonvolatile memory device, comprising:

• initiating a program suspend period by suspending a program operation;
• storing first data in a sensing latch of a first page buffer unit of a plurality of buffer units, the first data sensed from a selected memory cell;
• transferring, during the program suspend period, the first data from the sensing latch of the first page buffer unit to a sensing node line of a second page buffer unit of the plurality of buffer units;
• and
• performing an on-chip valley search (OVS) on the selected memory cell using the sensing latch,
• wherein, during the program suspend period, the plurality of page buffer units are occupied by write data of a suspended program operation.