Bias voltage schemes during pre-programming and programming phases

A memory device comprising:

• a memory array comprising a select gate, and a set of memory cells corresponding to a set of dummy wordlines, the set of dummy wordlines comprising a first dummy wordline adjacent to the select gate;
• and
• control logic, operatively coupled with the memory array, to perform memory programming operations comprising at least one of:
• causing a first bias voltage with respect to the first dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase;
• maintaining the first bias voltage at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase, wherein the first bias voltage is ramped from the power supply voltage to the first dummy wordline seed voltage;
• and
• causing, during a programming phase, the first bias voltage to be ramped from the first dummy wordline seed voltage to a program inhibit bias voltage.

A method comprising:

• causing, by a processing device, a bias voltage with respect to each dummy wordline of a set of dummy wordlines to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, wherein the set of dummy wordlines comprises a first dummy wordline adjacent to a select gate;
• causing, by the processing device, the bias voltage with respect to the first dummy wordline to be ramped from the power supply voltage to a first dummy wordline seed voltage;
• maintaining, by the processing device, the bias voltage with respect to the first dummy wordline at the first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase;
• and
• causing, by the processing device, the bias voltage with respect to the first dummy wordline to be ramped from the first dummy wordline seed voltage to a first program inhibit bias voltage in accordance with a first set of step-up voltage parameters, wherein the first set of step-up voltage parameters comprises a first step ratio defined based on a change in programming pulse voltage.