Semiconductor device and data storage system including the same

A semiconductor device comprising:

• a first chip structure;
• and
• a second chip structure on the first chip structure and including a memory cell array region,
• wherein the first chip structure includes:
• a semiconductor substrate having a first surface and a second surface opposing each other;
• a back side insulating layer below the second surface of the semiconductor substrate;
• an external input/output conductive pattern below the back side insulating layer;
• a first active region on the first surface of the semiconductor substrate;
• an isolation layer on the first surface of the semiconductor substrate and a side surface of the first active region;
• a transistor including a source/drain region within a first portion of the first active region and a gate structure on a second portion of the first active region;
• an interlayer insulating layer on the first active region and the isolation layer;
• an input/output connection wiring and a circuit wiring on the interlayer insulating layer;
• a source/drain contact plug penetrating through the interlayer insulating layer and electrically connected to the source/drain region and the circuit wiring;
• a first input/output contact plug penetrating through the interlayer insulating layer and electrically connected to the input/output connection wiring;
• and
• a through-electrode structure penetrating through the semiconductor substrate and the back side insulating layer and electrically connected to the first input/output contact plug and the external input/output conductive pattern,
• wherein the through-electrode structure includes a through-electrode and an insulating spacer on a side surface of the through-electrode,
• wherein a width of the through-electrode is greater than a width of the first input/output contact plug, and
• wherein a side surface of the first input/output contact plug includes:
• a lower side portion contacting the through-electrode;
• and
• an upper side portion contacting the interlayer insulating layer,
• wherein the through-electrode includes an electrode pattern and an electrode barrier layer covering a side surface and an upper surface of the electrode pattern, and
• wherein the electrode barrier layer contacts a lower surface of the first input/output contact plug and the lower side portion of the first input/output contact plug.

A data storage system comprising:

• a main substrate;
• a semiconductor device on the main substrate;
• and
• a controller electrically connected to the semiconductor device on the main substrate,
• wherein the semiconductor device includes:
• a first chip structure;
• and
• a second chip structure on the first chip structure and including a memory cell array region,
• wherein the first chip structure includes:
• a semiconductor substrate having a first surface and a second surface opposing each other;
• a back side insulating layer below the second surface of the semiconductor substrate;
• an external input/output conductive pattern below the back side insulating layer;
• a first active region on the first surface of the semiconductor substrate;
• an isolation layer on the first surface of the semiconductor substrate and a side surface of the first active region;
• a transistor including a source/drain region within a first portion of the first active region and a gate structure on a second portion of the first active region;
• an interlayer insulating layer on the first active region and the isolation layer;
• an input/output connection wiring and a circuit wiring on the interlayer insulating layer;
• a source/drain contact plug penetrating through the interlayer insulating layer and electrically connected to the source/drain region and the circuit wiring;
• a first input/output contact plug penetrating through the interlayer insulating layer and electrically connected to the input/output connection wiring;
• and
• a through-electrode structure penetrating through the semiconductor substrate and the back side insulating layer and electrically connected to the first input/output contact plug and the external input/output conductive pattern,
• wherein the through-electrode structure includes a through-electrode and an insulating spacer on a side surface of the through-electrode,
• wherein a width of the through-electrode is greater than a width of the first input/output contact plug, and
• wherein a side surface of the first input/output contact plug includes:
• a lower side portion contacting the through-electrode;
• and
• an upper side portion contacting the interlayer insulating layer,
• wherein the through-electrode includes an electrode pattern and an electrode barrier layer covering a side surface and an upper surface of the electrode pattern, and
• wherein the electrode barrier layer contacts a lower surface of the first input/output contact plug and the lower side portion of the first input/output contact plug.