Parallelized defect detection across multiple sub-blocks in a memory device

A method, comprising:

• selecting, by a processing device, a plurality of sub-blocks of a block of a memory device, wherein the block comprises a plurality of wordlines, a plurality of bitlines, and a plurality of strings, each string of the plurality of strings being connected to a respective bitline of the plurality of bitlines, wherein the block is divided into a plurality of sub-blocks comprising a first sub-block and a second sub-block, wherein each sub-block of the plurality of sub-blocks comprises a respective set of strings of the plurality of strings, and wherein each string of the set of strings is located at a sub-block position within its respective sub-block;
• causing, by the processing device, a first voltage to be applied to a dummy wordline of the plurality of wordlines, wherein the first voltage activates a first set of dummy cells associated with the dummy wordline and having a first state and deactivates a second set of cells associated with the dummy wordline and having a second state different from the first state, wherein each sub-block of the plurality of sub-blocks comprises a single string of the set of strings corresponding to an open string connected to a respective dummy cell of the first set of dummy cells and remaining strings of the set of strings each corresponding to a closed string connected to a respective dummy cell of the second set of dummy cells, and wherein the open string of the first sub-block is located at a different sub-block position than the open string of the second sub-block;
• and
• causing, by the processing device, a second voltage to be applied to a selected wordline of the plurality of wordlines, wherein the second voltage causes data to be read out from each open string to a respective page buffer of a plurality of page buffers.

A memory device comprising:

• a memory array comprising a block having a plurality of wordlines, a plurality of bitlines, and a plurality of strings, each string of the plurality of strings being connected to a respective bitline of the plurality of bitlines, wherein the block is divided into a plurality of sub-blocks comprising a first sub-block and a second sub-block, wherein each sub-block of the plurality of sub-blocks comprises a respective set of strings of the plurality of strings, and wherein each string of the set of strings is located at a sub-block position within its respective sub-block;
• and
• control logic, operatively coupled with the memory array, to perform operations comprising:
• causing a plurality of dummy cells to be programmed to have a dummy cell pattern to define a first set of dummy cells having a first state and a second set of dummy cells having a second state different from the first state, wherein the plurality of dummy cells is associated with a dummy wordline of the plurality of wordlines;
• and
• causing a defect detection operation to be performed in parallel across the plurality of sub-blocks in accordance with the dummy cell pattern.