Bank design with differential bulk bias in eFuse array
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Chia-En Huang
Life of this patent
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Abstract
A memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.
Claims20
A memory circuit comprising:
- a plurality of memory cells, each of the plurality of memory cells including a resistor and a transistor coupled to each other in series;
- and
- a sensing circuit including a read access transistor coupled to each of the plurality of memory cells, wherein respective bulk ports of the transistors of at least a first memory cell and a second memory cell of the plurality of memory cells are biased at different voltage levels, wherein, in response to the read access transistor receiving a read bit line voltage, the sensing circuit is configured to sense at least one of the first memory cell or the second memory cell.
A memory circuit comprising:
- a plurality of memory cells, each of the plurality of memory cells including a resistor and a transistor coupled to each other in series;
- and
- a write access transistor coupled to each of the plurality of memory cells, wherein respective bulk ports of the transistors of at least a first memory cell and a second memory cell of the plurality of memory cells are biased at different voltage levels, wherein, in response to the write access transistor receiving a write bit line voltage, a voltage source coupled to the write access transistor programs at least one of the first memory cell or the second memory cell.
A memory device comprising:
- a substrate including a first portion and a second portion disposed over the first portion;
- a first bulk electrode of a first word line (WL) transistor disposed over the second portion of the substrate;
- a deep n-well disposed over the first portion of the substrate;
- a pair of n-wells disposed over the deep n-well;
- a p-well disposed over the deep n-well and in between the pair of n-wells;
- a second bulk electrode of a second word line (WL) transistor disposed over the p-well;
- and
- a write access transistor coupled to each of the first bulk electrode and the second bulk electrode, wherein, in response to the write access transistor receiving a write bit line voltage, a voltage source coupled to the write access transistor provides a voltage signal to the first bulk electrode and the second bulk electrode.
Dependencies are inferred from the claim text.