Data transfer circuits in nonvolatile memory devices and nonvolatile memory devices including the same

A nonvolatile memory device comprising:

• a memory cell array including a plurality of memory cells;
• a page buffer circuit coupled to the memory cell array through a plurality of bit-lines;
• a data input/output (I/O) circuit configured to transmit/receive data to/from an external memory controller;
• a data transfer circuit (i) comprising a plurality of first repeaters connected to the data I/O circuit and (ii) connected between the page buffer circuit and the data I/O circuit, configured to:
• provide the data from the data I/O circuit to the page buffer circuit in a first operation mode;
• and
• provide the data from the page buffer circuit to the data I/O circuit in a second operation mode having a non-overlapping operating interval with the first operation mode;
• and
• a control circuit configured to control the page buffer circuit and the data transfer circuit,
• wherein the data transfer circuit is configured to float a portion of signal lines that do not transfer the data, from among a plurality of signal lines included therein, in response to a first power gating signal and a second power gating signal from the control circuit in each of the first operation mode and the second operation mode, and
• wherein the plurality of first repeaters include a first group of repeaters that are activated in the first operation mode and a second group of repeaters that are activated in the second operation mode.

A data transfer circuit in a nonvolatile memory device, the data transfer circuit comprising:

• a plurality of first repeaters connected to a first circuit element disposed in a data input/output (I/O) path of the nonvolatile memory device;
• a plurality of second repeaters connected to a second circuit element disposed in the data I/O path of the nonvolatile memory device, the second circuit element being spaced apart from the first circuit element;
• and
• a plurality of signal lines configured to connect the plurality of first repeaters and the plurality of second repeaters, the plurality of signal lines including a first group of signal lines and a second group of signal lines which are alternatingly arranged,
• wherein the plurality of first repeaters include:
• a first group of repeaters that are activated in a first operation mode;
• and
• a second group of repeaters that are activated in a second operation mode having a non-overlapping operating interval with the first operation mode,
• wherein the plurality of second repeaters include:
• a third group of repeaters that are activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines;
• and
• a fourth group of repeaters that are activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines,
• wherein, in the second operation mode, the first group of repeaters are configured to float a first output node coupled to the first group of signal lines in response to a first power gating signal, and
• wherein, in the first operation mode, the second group of repeaters are configured to float a second output node coupled to the second group of signal lines in response to a second power gating signal.