Memory circuit and method of operating same

A memory circuit comprising:

• a global bit line;
• a set of memory banks including a first memory bank, the first memory bank comprising:
• a first set of memory cells configured to store data;
• and
• a first local input output (LIO) circuit coupled to the global bit line and the first set of memory cells, the first LIO circuit comprising:
• a first driver circuit coupled to the global bit line, and configured to adjust a global bit line signal in response to at least a first signal, the first signal corresponds to a first value of the data stored in a first memory cell of the first set of memory cells;
• and
• a first booster circuit coupled to the global bit line, and configured to adjust a rising edge or a falling edge of the global bit line signal in response to a first delayed global bit line signal;
• and
• a global input output (GIO) circuit coupled to the first LIO circuit and the global bit line, and configured to output the first value of the data stored in the first memory cell of the first set of memory cells in response to the global bit line signal,
• wherein the first booster circuit comprises:
• a first inverter configured to generate a second signal in response to the global bit line signal, the first inverter including a first input terminal coupled to the global bit line, and a first output terminal;
• a delay circuit coupled to the first output terminal of the first inverter, and configured to generate a delayed second signal in response to the second signal;
• and
• a second inverter configured to generate a third signal in response to the delayed second signal, the second inverter including a second input terminal and a second output terminal, the second input terminal being coupled to an output terminal of the delay circuit, the third signal corresponds to the first delayed global bit line signal.

A method of operating a memory circuit, the method comprising:

• reading, by a local input output (LIO) circuit, a first memory cell in response to at least a sense amplifier signal, wherein reading the first memory cell comprises:
• sensing, by a sense amplifier, a first bit line signal and a second bit line signal in response to at least the sense amplifier signal, the sense amplifier being coupled to the first memory cell;
• generating, by a first inverter, an inverted second bit line signal in response to the second bit line signal, the inverted second bit line signal corresponding to the first bit line signal, the first inverter being coupled to the sense amplifier;
• setting, by a driver circuit, a global bit line signal on a global bit line in response to at least the first bit line signal or the inverted second bit line signal, the driver circuit being coupled to the global bit line, the sense amplifier and the first inverter;
• and
• causing, by a booster circuit, a rising edge or a falling edge of the global bit line signal to be adjusted in response to a delayed global bit line signal;
• and
• outputting, by a global input output (GIO) circuit a first value of datum stored in the first memory cell in response to the global bit line signal, the GIO circuit being coupled to the global bit line;
• wherein the booster circuit comprises:
• a second inverter configured to generate a first signal in response to the global bit line signal, the second inverter including a first input terminal coupled to the global bit line, and a first output terminal;
• a delay circuit coupled to the first output terminal of the second inverter, and configured to generate a delayed first signal in response to the first signal;
• and
• a third inverter configured to generate a second signal in response to the delayed first signal, the third inverter including a second input terminal and a second output terminal, the second input terminal being coupled to an output terminal of the delay circuit, the second signal corresponds to the delayed global bit line signal.