Non-volatile memory device

A non-volatile memory device, comprising:

• one or more memory blocks including
• a plurality of memory cells connected to a plurality of word lines, and
• a plurality of memory cell strings arranged in rows and columns;
• a page buffer unit including a plurality of page buffers that are connected to the plurality of memory cell strings, respectively, and include a plurality of buffer transistors;
• a monitoring buffer including a plurality of monitoring buffer transistors connected to the plurality of buffer transistors;
• a voltage generator that is configured to supply activation voltages to a first buffer transistor, in which a leakage current is to be measured, from among the plurality of buffer transistors, and to a first monitoring buffer transistor connected to the first buffer transistor;
• and
• a control logic that is configured to
• control the voltage generator to generate the activation voltages by using a voltage control signal, and
• detect the leakage current based on a monitoring voltage output from the first monitoring buffer transistor.

A non-volatile memory device, comprising:

• one or more memory blocks including a plurality of memory cells connected to a plurality of word lines, and a plurality of memory cell strings arranged in rows and columns;
• a page buffer unit including a plurality of page buffers that are connected to the plurality of memory cell strings, respectively, and include a plurality of buffer transistors;
• one or more pass units including a plurality of pass transistors that are configured to supply operation voltages to the plurality of word lines;
• one or more monitoring units including one or more monitoring pass transistors connected to the plurality of pass transistors;
• a row decoder that is configured to supply activation voltages to at least one of the plurality of pass transistors and the one or more monitoring pass transistors;
• a monitoring buffer including a plurality of monitoring buffer transistors connected to the plurality of buffer transistors;
• a voltage generator configured to supply activation voltages to, from among the plurality of pass transistors and the plurality of buffer transistors,
• a first pass transistor, in which a leakage current is to be measured, and to the one or more monitoring pass transistors, or
• a first buffer transistor, in which the leakage current is to be measured, and to a first monitoring buffer transistor connected to the first buffer transistor;
• and
• a control logic that is configured to control the voltage generator to generate the activation voltages by using a voltage control signal, and
• detect the leakage current based on monitoring voltages output from the one or more monitoring pass transistors or the first monitoring buffer transistor.