US 12,217,784 B2 · Boosted writeback voltage

Abstract

The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells.

Claims20

Dependent claims

A dynamic random access memory (DRAM) device, comprising:

digital logic circuitry to at least process column addresses and row addresses to retrieve data stored in a dynamic memory array, the digital logic circuitry to operate using a first digital logic supply voltage level;
and,
sense amplifier circuits that are part of the dynamic memory array to operate using the first digital logic supply voltage level during column operations and sense operations until a pair of cross-coupled inverters of the sense amplifier circuits reach a stable state using the first digital logic supply voltage and to operate, during writeback operations after the pair of cross-coupled inverters reach the stable state using the first digital logic supply voltage, using a boosted bitline voltage that is greater than the first digital logic supply voltage level.

A memory controller, comprising:

a command interface to communicate a first indicator and a second indicator to a memory device, based at least on the first indicator, the memory device to operate a plurality of sense amplifier circuits that are part of a dynamic memory array of the memory device using a first digital logic supply voltage level during a first column operation and a first sense operation that lasts at least until cross-coupled inverters of the plurality of sense amplifier circuits reach stable states using the first digital logic supply voltage, and to operate, during a first writeback operation that occurs after the first sense operation reaches the stable states using the first digital logic supply voltage to writeback data sensed by the first sense operation, using a first bitline voltage that is greater than the first digital logic supply voltage level, the memory device to, based at least on the second indicator, to operate, during a second writeback operation that occurs after a second sense operation reaches the stable states using the first digital logic supply voltage to writeback data sensed by the second sense operation, using a second bitline voltage that is equal to the first digital logic supply voltage level;
and,
a data interface to receive data sensed by the respective ones of the first plurality of sense operations.

Dependencies are inferred from the claim text.

Boosted writeback voltage

Life of this patent

Boosted writeback voltage

Life of this patent

Abstract

Claims20