US 12,217,781 B2 · Memory device and memory system

Abstract

According to one embodiment, a memory device includes: a first bank including a first memory cell; a second bank including a second memory cell; and a buffer circuit configured to temporarily stores data, wherein, during a read sequence for the first memory cell, the first bank is configured to: sense a first signal from the first memory cell, set the first memory cell to a reset state after the first signal is sensed, sense a second signal from the first memory cell in the reset state, determine first data stored in the first memory cell, based on the first signal and the second signal, and store the first data in the buffer circuit, and the second bank is configured to: write the first data in the buffer circuit to the second memory.

Claims19

Dependent claims

A memory device comprising:

a first bank including a first memory cell;
a second bank including a second memory cell;
and
a buffer circuit configured to temporarily stores data,
wherein, during a read sequence for the first memory cell,
the first bank is configured to:
sense a first signal from the first memory cell,
set the first memory cell to a reset state after the first signal is sensed,
sense a second signal from the first memory cell in the reset state,
determine first data stored in the first memory cell, based on the first signal and the second signal, and
store the first data in the buffer circuit, and
the second bank is configured to:
write the first data in the buffer circuit to the second memory.

10 more elements

A memory system comprising:

a memory device including a first bank including a plurality of first memory cells, a second bank including a plurality of second memory cells, and a buffer circuit configured to temporarily store data;
and
a controller configured to command a read sequence to the memory device,
wherein
when commanding the memory device to perform the read sequence for the first bank, the controller is configured to send to the memory device, a first address relating to the first bank, a first command commanding the read sequence, and a second address relating to the second address,
the memory device is configured to:
send first data from one or more memory cells included in the plurality of first memory cells and corresponding to the first address to the buffer circuit in response to the first command, and
write the first data in the buffer circuit to one or more memory cells included in the plurality of second memory cells and corresponding to the second address, before the first data is sent from the buffer circuit to the controller.

5 more elements

Dependencies are inferred from the claim text.

Memory device and memory system

Life of this patent

Memory device and memory system

Life of this patent

Abstract

Claims19