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US 12,217,717 B2Granted
Circuit and method for conditioning clock signal, display panel, and display device
AssigneeTcl China Star Optoelectronics Technology Co., Ltd.
InventorZhaoxian Zhong
Life of this patent
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Abstract
The present disclosure relates to a circuit and a method for conditioning a clock signal, display panel, and display device. The circuit includes a signal conversion circuit and a delay processing circuit; when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, the delay processing circuit receives the N-th clock signal transmitted from the N-th clock signal output terminal, and performs delay processing on the N-th clock signal, so as to avoid occurrence of GOA-stage transfer abnormality when one of the plurality of CK clock signals is in an abnormal condition that no signal is output.
Claims15
A clock signal conditioning circuit comprising:
- a signal conversion circuit, wherein an input terminal of the signal conversion circuit is configured to be connected to a (N+1)-th clock signal output terminal, an output terminal of the signal conversion circuit is configured to output a converted electrical signal, and the (N+1)-th clock signal output terminal is configured to be connected to the (N+1)-th stage GOA drive circuit;
- and a delay processing circuit configured to receive the converted electrical signal transmitted from the signal conversion circuit;
- wherein the delay processing circuit is further configured to receive an N-th clock signal transmitted from the N-th clock signal output terminal when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, perform delay processing on the N-th clock signal based on a preset interval clock signal, to obtain a delayed clock signal, and transmit the delayed clock signal to the (N+1)-th stage GOA drive circuit;
- and a timing of the delayed clock signal is the same as a timing of the (N+1)-th clock signal output from the (N+1)-th clock signal output terminal,
- wherein the delay processing circuit comprises:
- a switch circuit, wherein a control terminal of the switch circuit is configured to receive the converted electrical signal, and an input terminal of the switch circuit is configured to be connected to the N-th clock signal output terminal;
- and
- a delay circuit, wherein a first input terminal of the delay circuit is connected to the output terminal of the switch circuit, a second input terminal of the delay circuit is configured to receive a preset interval clock signal;
- the output terminal of the delay circuit is configured to be connected to the (N+1)-th stage GOA drive circuit, and
- wherein when no signal is output from the (N+1)-th clock signal output terminal, the voltage amplitude of the converted electrical signal falls within the turn-on threshold range of the switch circuit.
7 more elements
A display panel comprising a pixel unit, a GOA circuit, and a clock signal conditioning circuit;
- wherein the clock signal conditioning circuit is connected to the GOA circuit, and the GOA circuit is connected to the pixel unit;
- and
- wherein the clock signal conditioning circuit comprises:
- a signal conversion circuit, wherein an input terminal of the signal conversion circuit is configured to be connected to a (N+1)-th clock signal output terminal, an output terminal of the signal conversion circuit is configured to output a converted electrical signal, and the (N+1)-th clock signal output terminal is configured to be connected to the (N+1)-th stage GOA drive circuit;
- and
- a delay processing circuit configured to receive the converted electrical signal transmitted from the signal conversion circuit;
- wherein the delay processing circuit is further configured to receive an N-th clock signal transmitted from the N-th clock signal output terminal when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, perform delay processing on the N-th clock signal based on a preset interval clock signal, to obtain a delayed clock signal, and transmit the delayed clock signal to the (N+1)-th stage GOA drive circuit;
- and a timing of the delayed clock signal is the same as a timing of the (N+1)-th clock signal output from the (N+1)-th clock signal output terminal,
- wherein the delay processing circuit comprises:
- a switch circuit, wherein a control terminal of the switch circuit is configured to receive the converted electrical signal, and an input terminal of the switch circuit is configured to be connected to the N-th clock signal output terminal;
- and
- a delay circuit, wherein a first input terminal of the delay circuit is connected to the output terminal of the switch circuit, a second input terminal of the delay circuit is configured to receive a preset interval clock signal;
- the output terminal of the delay circuit is configured to be connected to the (N+1)-th stage GOA drive circuit, and
- wherein when no signal is output from the (N+1)-th clock signal output terminal, the voltage amplitude of the converted electrical signal falls within the turn-on threshold range of the switch circuit.
11 more elements
A display device comprising a display panel;
- the display panel comprises a pixel unit, a GOA circuit, and a clock signal conditioning circuit;
- the clock signal conditioning circuit is connected to the GOA circuit, and the GOA circuit is connected to the pixel unit;
- and
- wherein the clock signal conditioning circuit comprises:
- a signal conversion circuit, wherein an input terminal of the signal conversion circuit is configured to be connected to a (N+1)-th clock signal output terminal, an output terminal of the signal conversion circuit is configured to output a converted electrical signal, and the (N+1)-th clock signal output terminal is configured to be connected to the (N+1)-th stage GOA drive circuit;
- and
- a delay processing circuit configured to receive the converted electrical signal transmitted from the signal conversion circuit;
- wherein the delay processing circuit is further configured to receive an N-th clock signal transmitted from the N-th clock signal output terminal when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, perform delay processing on the N-th clock signal based on a preset interval clock signal, to obtain a delayed clock signal, and transmit the delayed clock signal to the (N+1)-th stage GOA drive circuit;
- and a timing of the delayed clock signal is the same as a timing of the (N+1)-th clock signal output from the (N+1)-th clock signal output terminal,
- wherein the delay processing circuit comprises:
- a switch circuit, wherein a control terminal of the switch circuit is configured to receive the converted electrical signal, and an input terminal of the switch circuit is configured to be connected to the N-th clock signal output terminal;
- and
- a delay circuit, wherein a first input terminal of the delay circuit is connected to the output terminal of the switch circuit, a second input terminal of the delay circuit is configured to receive a preset interval clock signal;
- the output terminal of the delay circuit is configured to be connected to the (N+1)-th stage GOA drive circuit, and
- wherein when no signal is output from the (N+1)-th clock signal output terminal, the voltage amplitude of the converted electrical signal falls within the turn-on threshold range of the switch circuit.
12 more elements
Dependencies are inferred from the claim text.