Pixel driving circuit, pixel driving method, and display panel for improving display uniformity through 7T2C pixel driving circuit

A pixel driving method applied to a pixel driving circuit comprising seven thin film transistors, two capacitors, and a light-emitting device,

• wherein a first one of the seven thin film transistors has a gate electrically connected to a first node, and a drain electrically connected to a second node;
• a second one of the seven thin film transistors has a drain electrically connected to the first node;
• a third one of the seven thin film transistors has a drain electrically connected to a source of the first thin film transistor;
• a fourth one of the seven thin film transistors has a source electrically connected to the second node;
• a fifth one of the seven thin film transistors has a source connected to the first node, and a drain electrically connected to the drain of the third thin film transistor;
• a sixth one of the seven thin film transistors has electrically connected to the first node;
• a seventh one of the seven thin film transistors has a drain electrically connected to the second node;
• a first one of the two capacitors has one end connected to the first node, and another end connected to the second node;
• a second one of the two capacitors has one end connected to the first node, and another end connected to the drain of the second thin film transistor;
• and
• the light-emitting device has a cathode connected to a source of the third thin film transistor;
• and the light-emitting device is driven by the first thin film transistor;
• and
• wherein the pixel driving method comprises:
• during an initialization stage, controlling all of a first scan signal received at a gate of the second thin film transistor, a third scan signal received at a gate of the six thin film transistor, and a fourth scan signal received at a gate of the seven thin film transistor to be at a high voltage level, and controlling all of a second scan signal received at a gate of the fifth thin film transistor, a light-emitting controlling signal received at a gate of the third thin film transistor and a gate of the fourth thin film transistor, and a data signal received at a source of the second thin film transistor to be at a low voltage level, so that a voltage level of the first node is a power voltage received at a source of the sixth thin film transistor and an anode of the light-emitting device, and a voltage level of the second node is a reference signal received at a source of the seventh thin film transistor;
• during a threshold voltage extraction stage, controlling all of the first scan signal, the second scan signal, and the fourth scan signal to be at the high voltage level, and controlling all of the third scan signal, the light-emitting controlling signal, and the data signal to be at the low voltage level, so that the voltage level of the first node is a sum of the reference signal and a threshold voltage, and the voltage level of the second node is the reference signal;
• during a data writing stage, controlling all of the first scan signal, the fourth scan signal, and the data signal to be at the high voltage level, and controlling all of the second scan signal, the third scan signal, and the light-emitting controlling signal to be at the low voltage level, so that the voltage level of the first node is a sum of a difference value between the high voltage level and the low voltage level of the data signal, and the reference signal and the threshold voltage, and the voltage level of the second node is the reference signal;
• and
• during a light-emitting stage, controlling the light-emitting controlling signal to be at the high voltage level, and controlling all of the first scan signal, the second scan signal, the third scan signal, the fourth scan signal, and the data signal to be at the low voltage level, so that the voltage level of the second node is a ground voltage received at a drain of the fourth thin transistor, and the voltage level of the first node is a sum of the difference value between the high voltage level and the low voltage level of the data signal, and the threshold voltage and the ground voltage.

A display panel, comprising a pixel driving circuit, the pixel driving circuit comprising a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, a first capacitor, a second capacitor, and a light-emitting device, the first thin film transistor configured as a driving thin film transistor of the light-emitting device;

• wherein a gate of the first thin film transistor is electrically connected to a first node, and a drain of the first thin film transistor is electrically connected to a second node;
• a gate of the second thin film transistor receives a first scan signal, a source of the second thin film transistor receives a data signal, a drain of the second thin film transistor is electrically connected to the first node;
• a gate of the third thin film transistor receives a light-emitting controlling signal, and a drain of the third thin film transistor is electrically connected to a source of the first thin film transistor;
• a gate of the fourth thin film transistor receives the light-emitting controlling signal, a source of the fourth thin film transistor is electrically connected to the second node, and a drain of the fourth thin film transistor receives a ground voltage;
• a gate of the fifth thin film transistor receives a second scan signal, a source of the fifth thin film transistor is connected to the first node, and a drain of the fifth thin film transistor is electrically connected to the drain of the third thin film transistor;
• a gate of the sixth thin film transistor receives a third scan signal, a source of the sixth thin film transistor receives a power voltage, and a drain of the sixth thin film transistor is electrically connected to the first node;
• a gate of the seventh thin film transistor receives a fourth scan signal, a source of the seventh thin film transistor receives a reference signal, and a drain of the seventh thin film transistor is electrically connected to the second node;
• one end of the first capacitor is electrically connected to the first node, and another end of the first capacitor is electrically connected to the second node;
• one end of the second capacitor is electrically connected to the first node, and another end of the second capacitor is electrically connected to the drain of the second thin film transistor;
• and
• an anode of the light-emitting device receives the power voltage, and a cathode of the light-emitting device is electrically connected to a source of the third thin film transistor,
• voltage levels of the first scan signal, the second scan signal, the third scan signal, the fourth scan signal, the light-emitting controlling signal, and the data signal are configured to form different voltage level combinations to correspond to an initialization stage, a threshold voltage extraction stage, a data writing stage, and a light-emitting stage in sequence.