Driving circuit, display substrate and display device

A driving circuit, comprising an output circuit, a first node reset circuit and a second node control capacitor;

• wherein
• the output circuit is configured to control a driving signal terminal to output a driving signal under the control of a potential of a first node;
• the first node reset circuit is configured to control to reset the first node under the control of a potential of a second node;
• the second node control capacitor is electrically connected to the second node;
• a width-to-length ratio of an output transistor included in the output circuit is less than or equal to a first predetermined width-to-length ratio;
• and/or a width-to-length ratio of a first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio;
• and/or, a capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value;
• a range of the first predetermined width-to-length ratio is greater than or equal to 150/3.8 and less than or equal to 230/3.8, and a range of the second predetermined width-to-length ratio is greater than or equal to 4/4.9 and less than or equal to 6/4.9;
• a range of the predetermined capacitance value is greater than or equal to 143fF and less than or equal to 243fF;
• wherein the driving circuit further comprises a third node control circuit, a fourth node control circuit, a fifth node control circuit, a second node control circuit, a first node control circuit, and an output reset circuit;
• the third node control circuit is respectively electrically connected to a second clock signal line, a first voltage line and a third node, and is configured to write a first voltage signal provided by the first voltage line into the third node under the control of a second clock signal provided by the second clock signal line;
• the fourth node control circuit is respectively electrically connected to a sixth node, a third clock signal line and a fourth node, and is configured to control the third clock signal line to write a third clock signal into the fourth node under the control of a potential of the sixth node, and control a potential of the fourth node according to the potential of the sixth node;
• the fifth node control circuit is electrically connected to the second clock signal line, a first clock signal line, an input terminal and a fifth node respectively, and is configured to control the input terminal to provide an input signal to the fifth node under the control of the second clock signal provided by the second clock signal line and a first clock signal provided by the first clock signal line;
• the second node control circuit is respectively electrically connected to a third node, a seventh node, a second voltage line, a second node and a third clock signal line, and is configured to control to connect the seventh node and the second voltage line under the control of a potential of the third node, and control to connect the seventh node and the third clock signal line under the control of the potential of the second node;
• a first electrode plate of the second node control capacitor is electrically connected to the seventh node, and a second electrode plate of the second node control capacitor is electrically connected to the second node;
• the first node control circuit is respectively electrically connected to the fourth node, the third clock signal line and the first node, and is configured to control to connect the fourth node and the first node under the control of the third clock signal provided by the third clock signal line;
• the output reset circuit is respectively electrically connected to the second node, the driving signal terminal and the first voltage line, and is configured to control to connect the driving signal terminal and the first voltage line under the control of the potential of the second node.