Multi-tile graphics processing unit

A system comprising:

• an interconnect to a system interface;
• and
• a multi-die graphics processor coupled with the interconnect, the multi-die graphics processor comprising:
• a package assembly comprising a plurality of distinct chiplets and a plurality of interconnect structures, the plurality of distinct chiplets including:
• a first chiplet comprising:
• a first semiconductor die including a first high-bandwidth memory (HBM) device;
• a second semiconductor die including a second HBM device;
• and
• a second chiplet comprising:
• a third semiconductor die coupled with the first semiconductor die and the second semiconductor die in a 2.5-dimensional (2.5D) arrangement, the third semiconductor die including a graphics processing resource and a cache coupled with the graphics processing resource,
• wherein,
• the cache is configured to cache data associated with memory accessed by the graphics processing resource, and
• the graphics processing resource includes a general-purpose graphics processor core and a tensor core.