Methods and apparatus to conditionally activate a big core in a computing system

A non-transitory computer readable medium comprising instructions which, when executed, cause one or more processors to at least:

• in response to a request to operate two or more processing devices as a single processing device, determine whether the two or more processing devices are available and capable of executing instructions according to the request;
• when the two or more processing devices are available and capable of executing the instructions:
• split the instructions into first sub-instructions and second sub-instructions;
• provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices;
• and
• generate an output for the instructions by combining a first output of the first processing device and a second output of the second processing device.

An apparatus to conditionally activate a big core in a computing system, the apparatus comprising:

• Interface circuitry to obtain a request to operate two or more processing devices as a single processing device;
• and
• processor circuitry including one or more of:
• at least one of a central processing unit, a graphic processing unit, or a digital signal processor, the at least one of the central processing unit, the graphic processing unit, or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus;
• a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations;
• or
• Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;
• the processor circuitry to perform at least one of the first operations, the second operations, or the third operations to instantiate:
• hardware management circuitry to:
• in response to the request, determine whether the two or more processing devices are available and capable of executing instructions according to the request;
• when the two or more processing devices are available and capable of executing the instructions:
• split the instructions into first sub-instructions and second sub-instructions;
• provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices;
• and
• generate an output for the instructions by combining a first output of the first processing device and a second output of the second processing device.