Integrated circuit chip apparatus
AssigneeCambricon Technologies Corporation Limited
InventorsShaoli Liu, Xinkai Song, Bingrui Wang, Yao Zhang, Shuai Hu
Life of this patent
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Abstract
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
Claims20
An integrated circuit chip apparatus comprising:
- a main processing circuit and a plurality of basic processing circuits, wherein
- the plurality of basic processing circuits are configured to perform a first set of neural network computations in parallel on data transferred by the main processing circuit to obtain a plurality of computation results, and transfer the plurality of computation results to the main processing circuit, and
- the main processing circuit is configured to perform a second set of neural network computations in series on the plurality of computation results.
A processing system, comprising:
- a neural network computing apparatus;
- a general interconnection interface;
- and
- a general-purpose processing apparatus connected to the neural network computing apparatus via the general interconnection interface,
- wherein the neural network computing apparatus further comprises:
- a main processing circuit and a plurality of basic processing circuits, wherein
- the plurality of basic processing circuits are configured to perform a first set of neural network computations in parallel on data transferred by the main processing circuit to obtain a plurality of computation results, and transfer the plurality of computation results to the main processing circuit, and
- the main processing circuit is configured to perform a second set of neural network computations in series on the plurality of computation results.
A method for performing neural network operations using an integrated circuit chip apparatus comprising a main processing circuit, and a plurality of basic processing circuits, the method comprising:
- performing, by the plurality of basic processing circuits, a first set of neural network computations in parallel on data transferred by the main processing circuit to obtain a plurality of computation results, and transfer the plurality of computation results to the main processing circuit, and
- performing, by the main processing circuit, a second set of neural network computations in series on the plurality of computation results.
Dependencies are inferred from the claim text.