Back to results
US 12,217,151 B2Granted
Layout parasitics and device parameter prediction using graph neural networks
AssigneeNVIDIA Corporation
InventorsHaoxing Ren, George Ferenc Kokai, Ting Ku, Walker Joseph Turner
Life of this patent
Estimating the term…
Abstract
A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
Claims18
A system comprising:
- at least one graph neural network;
- graph generation logic configured to transform a circuit netlist into a graph;
- and embedding logic configured to generate a node embedding for the graph in the at least one graph neural network, the node embedding formed by concatenating previously generated node embeddings with aggregated neighbor embeddings, the node embedding configured with different edge types of the graph grouped independently for processing by different attention layers of the at least one graph neural network, wherein the at least one graph neural network is configured to transform edges of the graph into parasitic resistance predictions for the circuit netlist.
A circuit simulator comprising:
- a graphics processing unit;
- at least one graph neural network;
- a non-transitory machine-readable media comprising instructions that, when applied to the graphics processing unit:
- generate a node embedding in a graph neural network for a graph representing a circuit, the node embedding formed by concatenating previously generated node embeddings with aggregated neighbor embeddings, the node embeddings configured with different edge types of the graph grouped independently for processing by different attention layers of the graph neural network;
- and operate the at least one graph neural network to transform edges of the graph into parasitic predictions for the circuit, wherein the instructions, when applied to the graphics processing unit, operate the at least one graph neural network to transform edges of the graph into parasitic resistance predictions for the circuit.
2 more elements
Dependencies are inferred from the claim text.