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US 12,217,129 B2Granted
Integrating circuit elements in a stacked quantum computing device
AssigneeGoogle Inc.
InventorsJulian Shaw Kelly, Joshua Yousouf Mutus
Life of this patent
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Abstract
A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.
Claims16
A method of bonding a first chip to a second chip, the method comprising:
- providing the first chip, wherein the first chip comprises a first dielectric substrate and a qubit device on the first dielectric substrate, wherein the qubit device comprises a first superconductor layer;
- providing the second chip, wherein the second chip comprises a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate and separate from the qubit readout element, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer;
- aligning the first chip to the second chip such that
- a portion of the control wire overlaps a first portion of the first superconductor layer the qubit,
- the qubit readout element overlaps a second portion of the first superconductor layer of the qubit device,
- and the shielding layer is arranged between the portion of the control wire and the portion of the first superconductor layer of the qubit device to reduce crosstalk between the control wire and the qubit device;
- and
- bonding the first chip to the second chip.
5 more elements
Dependencies are inferred from the claim text.