Latency sensitive workload balancing

A system for load balancing latency-sensitive tasks on isolated processors, comprising:

• a memory;
• and
• a processing device communicably coupled to the memory, the processing device to:
• identify one or more first tasks and one or more second tasks by an operating system of a computing device, wherein each of the second tasks is a latency-sensitive task characterized by one or more latency constraints;
• identify a priority level of each task of the one or more first tasks and a priority level of each task of the one or more second tasks;
• identify a first set of processors of the computing device, wherein the processors of the first set are non-isolated processors load balanced by a kernel scheduler of the operating system;
• assign, based on the priority level of each task of the one or more first tasks, a time slice to each task of the one or more first tasks, wherein a higher priority task corresponds to a larger time slice;
• schedule execution of the one or more first tasks on the first set of processors of the computing device, wherein each of the one or more first tasks is executed according to its respective assigned time slice;
• identify a second set of processors of the computing device, wherein the processors of the second set are isolated processors excluded from a scope of load balancing performed by the kernel scheduler;
• identify a first processor of the second set of processors in view of a number of latency-sensitive tasks scheduled to execute on each processor of the second set of processors and an amount of available processing capacity of each processor of the second set of processors, wherein the first processor of the second set of processors has a least number of latency-sensitive tasks scheduled to execute of the second set of processors and a greatest amount of available processing capacity of each processor of the second set of processors;
• identify, from the one or more second tasks, a next task in view of an amount of processor time that has been used by each of the one or more second tasks and the priority level of the next task;
• and
• execute one or more instructions of the next task on the first processor of the second set of processors.

A non-transitory machine-readable storage medium storing instructions for load balancing latency-sensitive tasks on isolated processors that cause a processing device to:

• identify one or more first tasks and one or more second tasks by an operating system of a computing device, wherein each of the second tasks is a latency-sensitive task characterized by one or more latency constraints;
• identify a priority level of each task of the one or more first tasks and a priority level of each task of the one or more second tasks;
• identify a first set of processors of the computing device, wherein the processors of the first set are non-isolated processors load balanced by a kernel scheduler of the operating system;
• assign, based on the priority level of each task of the one or more first tasks, a time slice to each task of the one or more first tasks, wherein a higher priority task corresponds to a larger time slice;
• schedule execution of the one or more first tasks on the first set of processors of the computing device, wherein each of the one or more first tasks is executed according to its respective assigned time slice;
• identify a second set of processors of the computing device, wherein the processors of the second set are isolated processors excluded from a scope of load balancing performed by the kernel scheduler;
• identify a first processor of the second set of processors in view of a number of latency-sensitive tasks scheduled to execute on each processor of the second set of processors and an amount of available processing capacity of each processor of the second set of processors, wherein the first processor of the second set of processors has a least number of latency-sensitive tasks scheduled to execute of the second set of processors and a greatest amount of available processing capacity of each processor of the second set of processors;
• identify, from the one or more second tasks, a next task in view of an amount of processor time that has been used by each of the one or more second tasks and the priority level of the next task;
• and
• execute one or more instructions of the next task on the first processor of the second set of processors.