Hardware acceleration for function processing

A system, comprising:

• a processor;
• memory in electronic communication with the processor;
• and
• instructions stored in the memory, the instructions being executable by the processor to perform operations of:
• receiving a first request to execute a first function from a first set of functions;
• analyzing first historical information related to a first plurality of requests received by a function processing service;
• based on analyzing the first historical information, configuring a set of hardware circuits to perform the first set of functions;
• receiving a second request to execute a second function from a second set of functions;
• analyzing second historical information related to a second plurality of requests received by the function processing service;
• and
• based on analyzing the second historical information configuring the set of hardware circuits to perform the second set of functions, wherein the second set of functions is different from the first set of functions.

A computer-implemented method, comprising:

• analyzing first historical information related to a first plurality of requests associated with a first set of functions and received by a function processing service during a first time interval;
• configuring a set of hardware circuits to perform the first set of functions during the first time interval based on the first historical information;
• analyzing second historical information related to a second plurality of requests associated with a second set of functions and received by the function processing service during a second time interval, wherein the second time interval is different from the first time interval;
• and
• configuring the set of hardware circuits to perform the second set of functions during the second time interval based on the second historical information, wherein the second set of functions is different from the first set of functions.