Processing unit with small footprint arithmetic logic unit
AssigneeAdvanced Micro Devices, Inc.
InventorsBin He, Shubh Shah, Michael Mantor
Life of this patent
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Abstract
A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.
Claims20
A method comprising:
- executing a plurality of mathematical operations with a plurality of operands using an arithmetic logic unit (ALU);
- and
- reducing a first operand and a second operand of the plurality of operands by discarding at least a portion of each of the first operand and the second operand, wherein the discarded portion of the first operand and the discarded portion of the second operand include different numbers of bits.
A processing unit, comprising:
- an arithmetic logic unit (ALU) configured to execute a plurality of mathematical operations with a plurality of operands,
- wherein the ALU is further configured to reduce a first operand and a second operand of the plurality of operands by discarding at least a portion of each of the first operand and the second operand, and wherein the discarded portion of the first operand and the discarded portion of the second operand include different numbers of bits.
A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:
- execute a plurality of mathematical operations with a plurality of operands using an arithmetic logic unit (ALU);
- and
- reduce a first operand and a second operand of the plurality of operands by discarding at least a portion of each of the first operand and the second operand, wherein the discarded portion of the first operand and the discarded portion of the second operand include different numbers of bits.
Dependencies are inferred from the claim text.