Method and architecture for performing modular addition and multiplication sequences

A computer-implemented method for performing addition and modular multiplication sequences comprising the steps of:

• providing a computer processing device having at least one arithmetic logic unit with at least one addition circuit and at least one modular multiplication circuit;
• performing, with the at least one arithmetic logic unit, quadratic extension field multiplication for use in an isogeny-based cryptosystem;
• receiving, within the at least one addition circuit, at least two numerical inputs and computing a sum utilizing addition operations of the at least one addition circuit;
• and
• receiving the sum, at least one other numerical input, and a numerical modulus within the at least one modular multiplication circuit and performing a modular multiplication operation as part of the quadratic extension field multiplication to generate a modular multiplication operation result without a conditional subtraction circuit in the at least one arithmetic logic unit.