Routing structure of semiconductor device and forming method thereof

A layout method, executed by at least one processor, the layout method comprising:

• generating a design layout by placing a cell, wherein the cell comprises:
• a first source/drain region and a second source/drain region in a first layer;
• a gate electrode extending in a first direction in a second layer, wherein the cell further includes a plurality of tracks extending in the first direction;
• a first power rail and a second power rail extending in a second direction perpendicular to the first direction in a third layer over the second layer, wherein the first power rail and the second power rail are on opposite sides of the cell;
• and
• a plurality of conductive segments extending in the second direction between the first and second power rails in the third layer, wherein the plurality of conductive segments comprises:
• a first conductive segment overlapping the first source/drain region from a top-view perspective and disposed immediately adjacent to the first power rail;
• a second conductive segment overlapping the second source/drain region from a top-view perspective and disposed immediately adjacent to the second power rail;
• a third conductive segment disposed between the first conductive segment and the second conductive segment;
• and
• a third power rail extending in the first direction in a fourth layer over the third layer, the third power rail occupying one of the plurality of tracks in the cell;
• and
• in response to the occupied one of the plurality of tracks, providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments extend in the first direction in the fourth layer and are both aligned with a single one of the plurality of tracks,
• wherein a number of the plurality of conductive segments is equal to or greater than a number of the plurality of tracks.

A layout method, executed by at least one processor, comprising:

• determining a number M of tracks extending in a first direction for a cell, wherein M is a natural number;
• receiving a design rule check (DRC) deck, the DRC deck including a minimal via spacing;
• generating a design layout by placing the cell, wherein the cell comprises:
• a transistor disposed in a transistor layer having a first source/drain region and a second source/drain region extending in a second direction, and a gate electrode extending in the first direction between the first source/drain region and the second source/drain region;
• a first power rail and a second power rail extending in the second direction in a first layer over the transistor layer, wherein the first power rail and the second power rail are disposed on opposite sides of the cell;
• and
• a plurality of first conductive segments extending in the second direction between the first and second power rails in the first layer;
• providing a third power rail extending in the first direction in a second layer over the first layer, the third power rail occupying one of the M tracks in the cell;
• in response to the occupied one of the M tracks, providing a number N of second conductive segments extending in the first direction in the second layer, N being a natural number greater than or equal to M, wherein each of the N second conductive segments corresponds to one of the M tracks and electrically connected to one of the first conductive segments, wherein two of the N second conductive segments are aligned to each other in the first direction and are both aligned with a single track of the M tracks;
• and
• providing N conductive vias to electrically couple first conductive segments to the corresponding second conductive segments, wherein any two of the N conductive vias are separated by a spacing substantially at least equal to the minimal via spacing.