Memory control apparatus, method for controlling memory control apparatus, and storage medium
AssigneeCanon Kabushiki Kaisha
InventorWataru Ochiai
Life of this patent
Estimating the term…
Abstract
A memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, includes an output unit configured to change an output mode of the clock signal for data transfer based on a memory access state and to output the clock signal for data transfer to the memory based on the output mode.
Claims13
A memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, and the memory control apparatus comprising:
- an output unit configured to change an output mode of the clock signal for data transfer based on a memory access state and to output the clock signal for data transfer to the memory based on the output mode,
- wherein in a busy state as the memory access state, the output unit sets a first output mode, and constantly outputs the clock signal for data transfer to the memory in the first output mode, and
- wherein in a non-busy state as the memory access state, the output unit sets a second output mode, and outputs the clock signal for data transfer to the memory as needed in the second output mode.
A method for controlling a memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, the method comprising:
- changing an output mode of the clock signal for data transfer based on a memory access state and outputting the clock signal for data transfer to the memory based on the output mode,
- wherein in a busy state as the memory access state, the changing sets a first output mode, and the outputting constantly outputs the clock signal for data transfer to the memory in the first output mode, and
- wherein in a non-busy state as the memory access state, the changing sets a second output mode, and the outputting outputs the clock signal for data transfer to the memory as needed in the second output mode.
A non-transitory storage medium storing a program causing a memory control apparatus configured to access a memory that involves synchronization of a clock signal for command transfer and a clock signal for data transfer with each other, the clock signal for command transfer and the clock signal for data transfer being independent of each other, to execute a control method, the control method comprising:
- changing an output mode of the clock signal for data transfer based on a memory access state and outputting the clock signal for data transfer to the memory based on the output mode,
- wherein in a busy state as the memory access state, the changing sets a first output mode, and the outputting constantly outputs the clock signal for data transfer to the memory in the first output mode, and
- wherein in a non-busy state as the memory access state, the changing sets a second output mode, and the outputting outputs the clock signal for data transfer to the memory as needed in the second output mode.
Dependencies are inferred from the claim text.