Data processing circuit and method, and semiconductor memory

A data processing circuit, comprising:

• a data selection module, configured to receive and output write data when a received write control command is in a first level state, or receive and output read data when a received read control command is in the first level state;
• wherein the read control command and the write control command are mutually exclusive signals, when a write operation is performed, the write control command is in the first level state and the read control command is in a fourth level state, when a read operation is performed, the read control command is in the first level state and the write control command is in the fourth level state;
• when one of the first level state and the fourth level state is at a high level, the other of the first level state and the fourth level state is at a low level;
• a check module, configured to receive the write data or the read data, check the write data or the read data, and obtain write check data or read check data, and output the write check data or the read check data;
• and
• a data output module, configured to receive the write check data or the read check data, output the write check data when the write control command is in the first level state, or output the read check data when the read control command is in the first level state;
• a sequence adjustment module, wherein the data selection module is connected to the check module through the sequence adjustment module, and the sequence adjustment module is configured to receive the write data or the read data outputted by the data selection module, perform a data transmission sequence adjustment operation on the write data or the read data according to a sequence adjustment control signal, and adjust the write data or the read data to a correct transmission sequence and then output it;
• and
• the check module is configured to:
• receive the write data adjusted to the correct transmission sequence or the read data adjusted to the correct transmission sequence, check the write data adjusted to the correct transmission sequence or the read data adjusted to the correct transmission sequence, and obtain write check data or read check data, and output the write check data or the read check data, wherein the data selection module is configured to transmit the write data or the read data of 2n bits to the sequence adjustment module within one data transmission cycle through n data lines, and among the 2n bits, an (n+1)-th bit to a 2n-th bit are transmitted in parallel, a first bit to an n-th bit are transmitted in parallel, an i-th bit and an (i+n)-th bit are serially transmitted by using a same data line, wherein n is a positive integer greater than or equal to 1, and i is a positive integer greater than or equal to 1 and less than or equal to n;
• the sequence adjustment module comprises n parallel sequence adjustment sub-modules, and each of the sequence adjustment sub-modules is provided with a data input terminal, a first output terminal, and a second output terminal, wherein, a data input terminal of an i-th sequence adjustment sub-module is connected to the data selection module for receiving an i-th bit and an (i+n)-th bit transmitted within each data transmission cycle, wherein i is a positive integer greater than or equal to 1 and less than or equal to n;
• the i-th sequence adjustment sub-module is configured to adjust a sequence of the i-th bit and a sequence of the (i+n)-th bit within each data transmission cycle to the correct transmission sequence, wherein, when the sequence adjustment control signal indicates that a data transmission sequence is reversed, the sequence of the i-th bit and the sequence of the (i+n)-th bit received within each data transmission cycle are interchanged, and when the sequence adjustment control signal indicates that the data transmission sequence is correct, the sequence of the i-th bit and the sequence of the (i+n)-th bit received within each data transmission cycle remain unchanged;
• and a first output terminal and a second output terminal of the i-th sequence adjustment sub-module are connected to the check module for respectively outputting, to the check module, the i-th bit adjusted to the correct transmission sequence and the (i+n)-th bit adjusted to the correct transmission sequence;
• wherein the i-th sequence adjustment sub-module comprises:
• a data processing unit, provided with an input terminal, a first output terminal, a second output terminal, and a control terminal, wherein the input terminal of the data processing unit is used as the data input terminal of the i-th sequence adjustment sub-module and configured to receive the i-th bit and the (i+n)-th bit serially transmitted within each data transmission cycle;
• the control terminal of the data processing unit is configured to receive a first clock signal, and in response to control of the first clock signal, the data processing unit is configured to generate, according to the i-th bit and the (i+n)-th bit received serially, first transmission data and second transmission data transmitted in parallel, the first transmission data comprising data of the (i+n)-th bit obtained by sampling at a second trigger edge of the first clock signal, and the second transmission data comprising data of the i-th bit obtained by sampling at the second trigger edge of the first clock signal;
• and the first output terminal and the second output terminal of the data processing unit are configured to output the first transmission data and the second transmission data in parallel;
• and a sequence adjustment unit, provided with a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first control terminal, and a second control terminal, wherein the first input terminal of the sequence adjustment unit is connected to the first output terminal of the data processing unit and configured to receive the first transmission data;
• the second input terminal of the sequence adjustment unit is connected to the second output terminal of the data processing unit and configured to receive the second transmission data;
• the first output terminal of the sequence adjustment unit is used as the first output terminal of the i-th sequence adjustment sub-module;
• the second output terminal of the sequence adjustment unit is used as the second output terminal of the i-th sequence adjustment sub-module;
• the first control terminal of the sequence adjustment unit is configured to receive the sequence adjustment control signal;
• the second control terminal of the sequence adjustment unit is configured to receive a second clock signal;
• the sequence adjustment unit performs sequence adjustment on the first transmission data and the second transmission data according to the sequence adjustment control signal and the second clock signal;
• when the sequence adjustment control signal indicates that the data transmission sequence is reversed, and the second clock signal is at a trigger level, the (i+n)-th bit in the first transmission data is outputted as high-order bit data through the first output terminal of the sequence adjustment unit, and the i-th bit in the second transmission data is outputted as low-order bit data through the second output terminal of the sequence adjustment unit;
• and when the sequence adjustment control signal indicates that the data transmission sequence is correct, and the second clock signal is at the trigger level, the i-th bit in the second transmission data is outputted as high-order bit data through the first output terminal of the sequence adjustment unit, and the (i+n)-th bit in the first transmission data is outputted as low-order bit data through the second output terminal of the sequence adjustment unit;
• wherein, a trigger level inversion moment of the second clock signal is aligned with an appearance moment of the second trigger edge of the first clock signal, and the trigger level inversion moment of the second clock signal is a moment at which the second clock signal is inverted from a non-trigger level to the trigger level.