Memory module and memory system including row hammer counter chip and operating method thereof

A memory system comprising:

• a memory module comprising a plurality of data chips and at least one row hammer counter chip, each of the plurality of data chips configured to store a data set corresponding to a plurality of burst lengths, and the at least one row hammer counter chip comprising a plurality of counter memory cells, each of the plurality of counter memory cells connected to a word line, among a plurality of word lines of the plurality of data chips;
• and
• a memory controller configured to count a number of times the word line, among the plurality of word lines, of each of the plurality of data chips is accessed during a row hammer monitoring time frame,
• wherein the at least one row hammer counter chip is configured to independently store in each of the plurality of counter memory cells connected to the word line, the number of times the word line is accessed for each of the plurality of data chips,
• wherein the plurality of counter memory cells comprises:
• a plurality of first word line cells connected to a first word line, among the plurality of word lines, and
• a plurality of second word line cells connected to a second word line, among the plurality of word lines, and
• wherein the plurality of first word line cells comprises:
• a plurality of first data chip cells dedicated for storing a number of times a first word line of a first data chip, among the plurality of data chips, is accessed, and
• a plurality of second data chip cells dedicated for storing a number of times a first word line of a second data chip, among the plurality of data chips, is accessed.

A method of operating a memory system comprising a memory module and a memory controller for controlling the memory module, wherein the memory module comprises a plurality of data chips and a row hammer counter chip comprising a plurality of counter memory cells, each of the plurality of counter memory cells connected to one of a plurality of word lines of the plurality of data chips, the method comprising:

• counting, by the memory controller, a number of times a word line, among the plurality of word lines, of each of the plurality of data chips is accessed during a row hammer monitoring time frame;
• and
• independently storing, by the memory controller, in each of the plurality of counter memory cells connected to the word line, the number of times the word line is accessed for each of the plurality of data chips,
• wherein the plurality of counter memory cells comprises:
• a plurality of first word line cells connected to a first word line, among the plurality of word lines, and
• a plurality of second word line cells connected to a second word line, among the plurality of word lines, and
• wherein the independently storing the number of times the word line is accessed for each of the plurality of data chips comprises:
• storing in a plurality of dedicated first data chip cells, among the plurality of first word line cells, a number of times a first word line of a first data chip, among the plurality of data chips, is accessed, and
• storing in a plurality of dedicated second data chip cells, among the plurality of first word line cells, a number of times a first word line of a second data chip, among the plurality of data chips, is accessed.