Method of improving programming operations in 3D NAND systems

A three-dimensional (3D) NAND memory device, comprising:

• a NAND string including a cell to be inhibited to program;
• a word line driver;
• a bit line driver;
• and
• a controller configured to control the word line driver and the bit line driver to:
• apply a first programming voltage signal to a word line to program a memory cell into a first programmed state;
• apply a first voltage to a bit line;
• subsequent to the applying the first voltage, perform a verify operation when the memory cell is in a second programmed state different from the first programmed state, wherein a second verify voltage of the second programmed state is lower than a first verify voltage of the first programmed state;
• determine a classification of the memory cell based on the verify operation;
• apply a second voltage to the bit line based on the determined classification;
• apply a second programming voltage signal to the word line to program the memory cell into the first programmed state;
• apply a third voltage to the bit line;
• apply a third programming voltage signal to the word line to program the memory cell into the first programmed state;
• and
• apply a fourth voltage to the bit line.

A non-transitory medium having instructions stored thereon that, upon execution by at least one controller, cause the at least one controller to perform a method of performing a programming operation of a memory device, the method comprising:

• applying a first programming voltage signal to a word line to program a memory cell into a first programmed state;
• applying a first voltage to a bit line;
• subsequent to the applying the first voltage, performing a verify operation when the memory cell is in a second programmed state different from the first programmed state, wherein a second verify voltage of the second programmed state is lower than a first verify voltage of the first programmed state;
• determining a classification of the memory cell based on the verify operation;
• applying a second voltage to the bit line based on the determined classification;
• applying a second programming voltage signal to the word line to program the memory cell into the first programmed state;
• applying a third voltage to the bit line;
• applying a third programming voltage signal to the word line to program the memory cell into the first programmed state;
• and
• applying a fourth voltage to the bit line.