Fingerprint sensor and display device including the same

A fingerprint sensor comprising:

• at least one sensor pixel arranged in a sensing area,
• wherein the sensor pixel includes:
• a pixel electrode coupled to a first node;
• a first transistor including a source electrode and a drain electrode, the first transistor being coupled between the first node and a first power line, the first transistor including a first gate electrode coupled to a first scan line and a second gate electrode opposite to the first gate electrode, the second gate electrode being coupled to the first power line;
• a first capacitor coupled between the first node and a second scan line, and comprising a first electrode and a second electrode, the second electrode comprising a portion of the pixel electrode;
• a second transistor coupled between a readout line and a second power line, the second transistor including a first gate electrode coupled to the first node and a second gate electrode opposite to the first gate electrode;
• and
• a third transistor coupled between the second transistor and the second power line, the third transistor including a first gate electrode coupled to the second scan line and a second gate electrode opposite to the first gate electrode,
• wherein the source electrode of the first transistor is directly connected to the second gate electrode of the first transistor and the first power line,
• wherein the drain electrode of the first transistor is directly connected to the pixel electrode and is electrically connected to the second electrode of the first capacitor.

A display device comprising:

• a display panel including display pixels arranged in a display area;
• and
• a fingerprint sensor including scan lines, readout lines, at least one power line, and sensor pixels, which are arranged in a sensing area,
• wherein at least one of the sensor pixels includes:
• a pixel electrode coupled to a first node;
• a first transistor including a source electrode and a drain electrode, the first transistor being coupled between the first node and a first power line, the first transistor including a first gate electrode coupled to a first scan line and a second gate electrode opposite to the first gate electrode, the second gate electrode being coupled to the first power line;
• a first capacitor coupled between the first node and a second scan line;
• a second transistor coupled between a readout line and a second power line, the second transistor including a first gate electrode coupled to the first node and a second gate electrode opposite to the first gate electrode;
• and
• a third transistor coupled between the second transistor and the second power line, the third transistor including a first gate electrode coupled to the second scan line and a second gate electrode opposite to the first gate electrode,
• wherein the source electrode of the first transistor is electrically connected to the second gate electrode of the first transistor and the first power line,
• wherein the drain electrode of the first transistor is electrically connected to the pixel electrode and a second electrode of the first capacitor,
• wherein the first transistor is electrically coupled between the first power line and the pixel electrode along a first current path, and the second transistor is electrically coupled between the readout line and the second power line along a second current path separate from the first current path, and
• wherein the drain electrode of the first transistor is electrically coupled between the pixel electrode and the source electrode of the first transistor.