Machine learning attack resistant strong PUF with dual-edge sampling function

A machine learning attack resistant strong PUF with a dual-edge sampling function characterized in that comprises N switch units, wherein each switch unit has a first input terminal, a second input terminal, a control terminal, a first output terminal and a second output terminal;

• a challenge signal is input to the control terminal of each of the switch unit;
• each of the switch unit is able to transmit square signals input to the first input terminal and the second input terminal of each of the switch unit to the first output terminal and the second output terminal of each of the switch unit in parallel or in a crossed manner under the control of the challenge signal input to the control terminal of each of the switch unit and output the square signals by the first output terminal and the second output terminal of each of the switch unit;
• the first output terminal of the nth switch unit is connected to the first input terminal of the (n+1)th switch unit, the second output terminal of the nth switch unit is connected to the second input terminal of the (n+1)th switch unit, and n=1, 2, . . . , N−1;
• the machine learning attack resistant strong PUF with a dual-edge sampling function further comprises two arbiters, which are referred to as a first arbiter and a second arbiter respectively, the first arbiter and the second arbiter each have a first input terminal, a second input terminal and an output terminal, the first output terminal of the Nth switch unit is connected to the first input terminal of the first arbiter and the first input terminal of the second arbiter, the second output terminal of the Nth switch unit is connected to the second input terminal of the first arbiter and the second input terminal of the second arbiter, the first arbiter is used for determining a sequential order of delays at a rising edge of signals input to the first input terminal and the second input terminal of the first arbiter and generating a corresponding signal which is output by the output terminal of the first arbiter, and the second arbiter is used for determining a sequential order of delays at a falling edge of signals input to the first input terminal and the second input terminal of the second arbiter and generating a corresponding signal which is output by the output terminal of the second arbiter;
• each switch unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor, wherein a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected, and a connecting terminal is the first input terminal In0 of the switch unit;
• a supply voltage VDD is accessed to a source of the first PMOS transistor, a source of the fourth PMOS transistor, a source of the fifth PMOS transistor and a source of the eighth PMOS transistor;
• a drain of the first PMOS transistor, a drain of the first NMOS transistor, a gate of the second PMOS transistor, a source of the second PMOS transistor, a gate of the second NMOS transistor and a source of the second NMOS transistor are connected;
• a drain of the second PMOS transistor, a drain of the second NMOS transistor, a source of the third PMOS transistor and a source of the third NMOS transistor are connected;
• a gate of the third PMOS transistor, a gate of the third NMOS transistor, a gate of the seventh PMOS transistor and a gate of the seventh NMOS transistor are connected, and a connecting terminal is the control terminal Ci of the switch unit;
• a drain of the third PMOS transistor, a drain of the seventh NMOS transistor, a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor are connected;
• a drain of the third NMOS transistor, a drain of the seventh PMOS transistor, a gate of the eighth NMOS transistor and a gate of the eighth PMOS transistor are connected;
• a drain of the fourth PMOS transistor and a drain of the fourth NMOS transistor are connected, and a connecting terminal is the first output terminal Out0 of the switch unit;
• a source of the first NMOS transistor, a source of the fourth NMOS transistor, a source of the fifth NMOS transistor and a source of the eighth NMOS transistor are all grounded;
• a gate of the fifth PMOS transistor and a gate of the fifth NMOS transistor are connected, and a connecting terminal is the second input terminal In1 of the switch unit;
• a drain of the fifth PMOS transistor, a drain of the fifth NMOS transistor, a gate of the sixth PMOS transistor, a drain of the sixth PMOS transistor, a gate of the sixth NMOS transistor and a source of the sixth NMOS transistor are connected;
• a drain of the sixth PMOS transistor, a drain of the sixth NMOS transistor, a source of the seventh PMOS transistor and a source of the seventh NMOS transistor are connected;
• and a drain of the eighth PMOS transistor and a drain of the eighth NMOS transistor are connected, and a connecting terminal is the second output terminal Out1 of the switch unit.