Artificial intelligence chip and artificial intelligence chip-based data processing method

An artificial intelligence (AI) chip-based data processing method, comprising:

• calculating, on a basis of one of at least one operation node corresponding to an AI algorithm, data to be processed and outputting a calculation result by each of at least one calculation module in a data flow network, the data flow network being configured to process, on a basis of the AI algorithm, the data to be processed;
• and
• receiving, by a next transfer module corresponding to each calculation module, the calculation result output by each calculation module and processing the calculation result, the next transfer module being connected to each calculation module,
• wherein the data to be processed flows in the data flow network according to a preset data flow direction;
• wherein a control flow dam is disposed between each calculation module and the next transfer module, the method further comprising:
• controlling, by the control flow dam, a flow of the calculation result from each calculation module to the next transfer module;
• wherein the control flow dam comprises a write end, a read end, a full-load end, and a no-load end, and further comprises:
• a first AND gate, a second AND gate, a first NOT gate, and a second NOT gate;
• the first AND gate is connected to the write end to constitute an uplink valid end, the second AND gate is connected to the read end to constitute a downlink permission end, the first NOT gate is connected to the full-load end to constitute an uplink permission end, and the second NOT gate is connected to the no-load end to constitute a downlink valid end, the method further comprising:
• receiving, by the uplink valid end, a first valid signal transmitted by each calculation module;
• receiving, by the downlink permission end, the second permission signal transmitted by the next transfer module;
• transmitting, by the first uplink permission end, a first permission signal to each calculation module and the first AND gate;
• and
• transmitting, by the downlink valid end, a second valid signal to the next transfer module and the second AND gate.