Computational array microprocessor system using non-consecutive data formatting

A microprocessor system, comprising:

• a computational array that includes a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value of a group of values addressed from memory and a first portion of the group of values operated by the plurality of computation units are synchronously provided together to the computational array to be processed in parallel in a first computation processing;
• and
• a hardware data formatter configured to, based on a stride, provide the first portion of the group of values to the computational array for the first computation processing and identify a second portion of the group of values not provided for the first computation processing, wherein the hardware data formatter is configured to perform a cache check to obtain the first portion of the group of values,
• and wherein the second portion of the group of values are stored and provided, by the hardware data formatter, to the computational array for a second computation processing subsequent to the first computation processing.