ZQ calibration circuit and method for memory interfaces

A memory device, the memory device comprising:

• an on-chip calibration device coupled to a reference node;
• a plurality of variable impedance circuits coupled to a plurality of nodes;
• first circuitry configured to supply a reference voltage at the reference node based on a current in the on-chip calibration device;
• second circuitry comprising a plurality of switches coupled to the plurality of nodes and configured to change the second circuitry between a plurality of configurations, the second circuitry configured to establish, for each configuration, a calibration voltage at one of the plurality of nodes based on current in one of plurality of variable impedance circuits connected to the respective one of the plurality of nodes;
• a comparator circuit switchably connected to the reference node and the plurality of nodes and configured, for each configuration of the second circuitry, to compare the respective calibration voltage to the reference voltage;
• and
• third circuitry configured to perform ZQ calibration for each configuration of the second circuitry, based on the comparison of the respective calibration to the reference voltage.

A method comprising:

• responsive to a ZQ calibration start command, activating a calibration circuitry and passing current from a first calibration node through a first variable impedance circuit of the calibration circuitry, wherein the calibration circuitry comprises an on-chip calibration device coupled to a reference node;
• calibrating a first impedance value of the first variable impedance circuit based on a comparison of a first calibration voltage at the first calibration node to a reference voltage at the reference node;
• responsive to a signal indicative that the calibration of the first impedance value is complete, disconnecting the first variable impedance circuit and passing current from a second calibration node through a second variable impedance circuit of the calibration circuitry;
• calibrating a second impedance value of the second variable impedance circuit based on a comparison of a second calibration voltage at the second calibration node to a reference voltage at the reference node;
• and
• responsive to a ZQ calibration latch command, latching the first impedance value into a first register of a first termination device and the second impedance value into a second register of a second termination device.