Read arbiter circuit with dual memory rank support

A method, comprising:

• receiving, by a memory control circuit, a plurality of read requests for a plurality of memory ranks including a given memory rank that includes a plurality of memory circuits coupled to a common communication bus, wherein the plurality of read requests includes a first subset of read requests to a first memory rank of the plurality of memory ranks, and a second subset of read requests to a second memory rank of the plurality of memory ranks;
• allocating, by the memory control circuit and based on respective numbers of requests in the first subset and the second subset, a first number of slots of a total number of slots for read requests included in the first subset, and a second number of slots of the total number of slots for read request included in the second subset, wherein the total number of slots corresponds to a maximum number of read accesses that can be performed in a read turn;
• and
• determining, by the memory control circuit in response to an initiation of the read turn to the plurality of memory ranks, a number of rank switches between the first memory rank and the second memory rank based on at least one quality-of-service requirement associated with the plurality of read requests.

A non-transitory computer-readable storage medium having design information stored thereon, wherein the design information specifies a design of at least a portion of a hardware integrated circuit in format recognized by a semiconductor manufacturing system that is configured to use the design information to produce the hardware integrated circuit according to the design information, wherein the design information specifies that the hardware integrated circuit comprises:

• a memory control circuit configured to:
• receive a plurality of read requests for a plurality of memory ranks including a given memory rank that includes a plurality of memory circuits coupled to a common communication bus, wherein the plurality of read requests includes a first subset of read requests to a first memory rank of the plurality of memory ranks, and a second subset of read requests to a second memory rank of the plurality of memory ranks;
• in response to an initiation of a read turn to the plurality of memory ranks, allocate, based on respective numbers of requests in the first subset and the second subset, a first number of slots of a total number of slots for read requests included in the first subset, and a second number of slots of the total number of slots for read request included in the second subset;
• determine, for the read turn, a number of rank switches between the first memory rank and the second memory rank based on at least one quality-of-service requirement associated with the plurality of read requests;
• and
• perform allocated read requests during the read turn using the number of rank switches.