Atomic compare and swap in a coherent cache system

A device comprising:

• a processor configured to:
• receive a processor instruction;
• and
• based on the processor instruction, provide a memory operation that specifies a value, an address, and a first set of data;
• a cache controller coupled to the processor;
• a tag memory coupled to the cache controller;
• a store queue coupled to the cache controller;
• and
• a first cache memory coupled to the store queue, wherein the cache controller is configured to, based on the memory operation:
• determine whether the address is associated with a hit in the first cache memory;
• based on the address being associated with a hit, determine whether to retrieve a second set of data from the first cache memory or a second cache memory based on a state stored in the tag memory and associated with the address;
• and
• cause the store queue to:
• determine whether the second set of data corresponds to the value;
• and
• based on whether the second set of data corresponds to the value, determine whether to store the first set of data in the first cache memory.