Semiconductor chip for correcting aligned error, semiconductor system for correcting aligned error, and method for correcting aligned error

A semiconductor system for correcting an aligned error, comprising:

• a memory chip including a first memory, configured to write coded data to the first memory or read transformed transmission data in which the coded data is transformed by an operating environment of the first memory;
• and
• a control chip including an Error Correction Code (ECC) circuit,
• wherein the ECC circuit is configured to obtain data, encode the obtained data by multiplying the obtained data by a generator matrix of ECC which was generated previously, store the encoded target data in the memory chip, obtain the transformed transmission data from the first memory of the memory chip, and generate an error corrected data by correcting single errors of the transformed transmission data and a plurality of double adjacent errors that do not exceed a first value boundary of a predetermined number of bits by using a parity check matrix of the ECC and output the error corrected data.

A method for correcting an aligned error performed by a semiconductor system including a memory chip including a first memory, and a control chip including an Error Correction Code (ECC) circuit for controlling the memory chip, comprising:

• obtaining target data to be encoded, and encoding the target data by multiplying a generator matrix of an ECC which was generated previously;
• storing the encoded target data in the first memory of the memory chip;
• reading the encoded target data from the first memory of the memory chip or reading transformed transmission data which was transformed during transmission;
• and
• generating an error corrected data by correcting single errors of the transformed transmission data and a plurality of double adjacent errors that does not exceed a first value boundary of a predetermined number of bits by using a parity check matrix of the ECC and outputting the error corrected data.