Storage system and method for hiding error checking and correcting (ECC) encoding delay

A storage system for hiding error checking and correcting (ECC) encoding delay, comprising:

• a static random access memory (SRAM), which includes a data input, a write signal input, a read signal input and a data output;
• a write register module, which is configured to output a write signal;
• an intermediate write register module, which is configured to receive the write signal from the write data register module and then transmit the write signal to the write signal input of the SRAM;
• a write data register, which is configured to output write data;
• an ECC coding module, which is configured to receive the write data from the write data register and to generate an ECC check code in view of the write data;
• an intermediate write data register, which is configured to:
• receive the write data from the write data register;
• receive the ECC check code from the ECC coding module;
• and
• transmit the write data and the ECC check code to the data input of the SRAM;
• a bypass register module, which is configured to receive the write data from the intermediate write data register;
• a read register module, which is configured to transmit a read signal to the read signal input of the SRAM;
• an ECC encoding error checking module, which is configured to:
• read a data set and the ECC check code from the SRAM through the data output of the SRAM;
• check the data set;
• and
• correct errors in the data set in view of the data set and the ECC check code;
• a read data selector, which includes a first input and a second input, wherein:
• the first input is configured to receive the write data from the bypass register module;
• the second input is configured to receive from the ECC encoding error checking module the data set which is read from the SRAM;
• and
• the read data selector is configured to output what is selected from one of what is received by the first input and what is received by the second input;
• and
• a read data register, which is configured to receive what is outputted from the read data selector, wherein:
• when a timing sequence of the intermediate write register module aligns with a timing sequence of the intermediate write data register:
• the intermediate write register module is configured to transmit the write signal to the write signal input of the SRAM;
• the intermediate write data register is configured to, in concurrence with transmission to the write signal input of the SRAM of the write signal by
• the intermediate write register module, transmit the write data to the data input of the SRAM;
• and
• the read register module is configured to transmit the read signal to the read signal input of the SRAM;
• and
• in response to the read signal and the write signal:
• when data at an address is read right after the data is written to the address, the read data selector is configured to select to output the write data received from the bypass register module;
• but
• when data is written to an address but data at an other address is read, a data set selector is configured to select to output the data set whose errors have been checked and corrected by the ECC encoding error checking module which reads the data set from the SRAM.