Error detection, prediction and handling techniques for system-in-package memory architectures

A system comprising:

• a host;
• a reliability availability serviceability (RAS) non-volatile memory (NVM);
• and
• a system-in-package (SIP) including:
• one or more memory dice including:
• a memory array arranged in a plurality of blocks;
• an electronic fuse (eFuse) module configured to store memory health information of the one or more memory dice;
• and
• a D-Flag register configured to store on-die memory error information of the one or more memory dice;
• and
• a logic die including:
• computation logic;
• a memory controller configured to communicatively couple the computation logic to the one or more memory dice, wherein the memory controller includes an S-Flag register configured to store system memory error information and a read address buffer configured to store memory read addresses;
• a RAS memory management unit (MMU) configured to communicatively couple the memory controller to a host, wherein the RAS MMU is configured to manage memory error detection, memory error prediction and memory error handling based on the memory health information, the on-die memory error information, the system memory error information and the memory read addresses;
• and
• a non-volatile memory interface communicatively coupling to the RAS MMU to the RAS non-volatile memory.