BMC time management method, system and apparatus, and computer medium

A Baseboard Management Controller (BMC) time management method, performed by a BMC and comprising:

• sending time loss information to a Central Processing Unit (CPU) after detecting a loss of time of the BMC, so that the CPU sends, after receiving the time loss information, a notification of executing a time recovery operation to a Basic Input Output System (BIOS);
• receiving time information that is synchronized by the BIOS after receiving the notification of executing the time recovery operation, wherein the time information comprises time information obtained in a Complementary Metal Oxide Semiconductor (CMOS) by the BIOS;
• and
• recovering the time of the BMC based on the time information;
• wherein the BMC is configured to send the time loss information to the CPU by changing a state of a first pin installed on the BMC;
• and
• the CPU is configured to receive the time loss information by detecting a change in a state of a second pin installed on the CPU,
• wherein the state of the first pin is associated with the state of the second pin.

A Baseboard Management Controller (BMC) time management method, performed by a CPU and comprising:

• receiving time loss information sent by a BMC;
• and
• sending a notification of executing a time recovery operation to a BIOS, so that the BIOS synchronizes time information to the BMC after receiving the notification of executing the time recovery operation, and then the BMC recovers time of the BMC based on the time information,
• wherein the time loss information comprises information that is sent by the BMC after detecting a loss of the time of the BMC;
• and the time information comprises time information obtained in a Complementary Metal Oxide Semiconductor (CMOS) by the BIOS;
• wherein the BMC is configured to send the time loss information to the CPU by changing a state of a first pin installed on the BMC;
• and
• the CPU is configured to receive the time loss information by detecting a change in a state of a second pin installed on the CPU,
• wherein the state of the first pin is associated with the state of the second pin.