Systems and methods for asynchronous finite machines

A method comprising:

• triggering, by a clockless trigger circuit, a first trigger signal in response to a first-state asynchronous event signal being asserted;
• providing, by a clockless virtual clock-pulse circuit, a first virtual-clock event to an asynchronous finite state machine;
• generating, by the asynchronous finite state machine, a retimed first-state asynchronous event signal in response to receiving a first pulse of the first virtual-clock event and a first-state event signal;
• transitioning the asynchronous finite state machine from a first state to a second state in response to the retimed first-state asynchronous event signal and to the first virtual-clock event;
• triggering, by the clockless trigger circuit, a second trigger signal in response to receiving a second-state asynchronous event signal;
• providing, by the clockless virtual clock-pulse circuit, a second virtual-clock event to the asynchronous finite state machine;
• generating, by the asynchronous finite state machine, a retimed second-state asynchronous event signal in response to receiving a first pulse of the second virtual-clock event and the second-state asynchronous event signal;
• and
• transitioning the asynchronous finite state machine from the second state to a third state in response to the retimed second-state asynchronous event signal and to the second virtual-clock event.

A system comprising:

• a clockless trigger circuit comprising a first-state asynchronous event input to receive a first-state asynchronous event signal, and a second-state asynchronous event input to receive a second-state asynchronous event signal, wherein the clockless trigger circuit is configured to:
• assert a first trigger signal in response to the first-state asynchronous event signal being asserted while an asynchronous finite state machine is in a first state;
• and
• assert a second trigger signal when the second-state asynchronous event signal is asserted while the asynchronous finite state machine is in a second state;
• a clockless virtual clock-pulse circuit coupled to the clockless trigger circuit, and configured to receive the first and second trigger signals and generate first and second virtual-clock events in response to the first and second trigger signals, respectively, being asserted;
• and
• the asynchronous finite state machine, coupled to the clockless trigger circuit and the clockless virtual clock-pulse circuit, and configured to:
• generate a retimed first-state asynchronous event signal in response to receiving a first pulse of the first virtual-clock event while in the first state;
• transition from the first state to a first intermediate state in response to the retimed first-state asynchronous event signal;
• transition from the first intermediate state to the second state in response to receiving a second pulse of the first virtual-clock event while in the first intermediate state;
• generate a retimed second-state asynchronous event signal in response to receiving a first pulse of the second virtual-clock event while in the second state;
• transition from the second state to a second intermediate state in response to the retimed second-state asynchronous event signal;
• and
• transition from the second intermediate state to a third state in response to receiving a second pulse of the second virtual-clock event while in the second intermediate state.