US 12,216,226 B2Granted

Radar system

AssigneeNXP B.V.

InventorsUlrich Moehlmann, Cristian Pavao Moreira, Andreas Johannes Köllmann

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Abstract

Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).

Claims20

Dependent claims

A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising:

a phase comparator connected to receive the first clock signal and a feedback signal;
a loop filter connected to receive an output signal from the phase comparator;
a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency;
a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency;
a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator;
and
a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal;
wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and
wherein the divide by n clock divider comprises five flip-flops, FFs, arranged to receive the second clock signal from the second oscillator, three OR gates and one AND gate arranged to receive outputs from the FFs.

6 more elements

a phase comparator connected to receive the first clock signal and a feedback signal;
a loop filter connected to receive an output signal from the phase comparator;
a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency;
a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency;
a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator;
and
a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal;
wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and
wherein the divide by n clock divider comprises eight FFs arranged to receive the second clock signal from the second oscillator and six OR gates arranged to receive outputs from the FFs and provide the 2n phase shifted clock signals.

6 more elements

a phase comparator connected to receive the first clock signal and a feedback signal;
a loop filter connected to receive an output signal from the phase comparator;
a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency;
a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency;
a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator;
and
a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal;
wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and
wherein the divide by n clock divider comprises five FFs arranged to receive the second clock signal from the second oscillator, three OR gates arranged to receive outputs from the FFs and provide n of the 2n phase shifted clock signals and three AND gates arranged to receive outputs from the FFs and provide another n of the 2n phase shifted clock signals.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/661,944Filed 4 May 2022
Priority: EP 2130562812 May 2021
Published: US 2022/0365173 A117 Nov 2022
Granted: 4 Feb 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

G01S 7/40
Of systems according to group G01S13/00: means for monitoring or calibrating
H03L 7/18
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop:…
G01S 7/032
Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver: constructional details for solid-state radar subsystems
G01S 7/35
Of systems according to group G01S13/00: details of non-pulse systems

Family

US 2022/0365173 A1Pre-grant publication · published 17 Nov 2022
US 12,216,226 B2This patent

From the US filing history. Foreign family members aren’t listed.

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