Output voltage glitch reduction in test systems

An automated testing system, the system comprising:

• a switch circuit coupled to an input/output (I/O) connection of the system;
• a force amplifier (FA) coupled to the switch circuit;
• a first adjustable current clamp circuit coupled to an output transistor of the FA, the first adjustable current clamp circuit including:
• a replica transistor coupled as a current mirror pair to the output transistor of the FA, wherein the replica transistor is a field effect transistor (FET) and is scaled in size to the output transistor by a size ratio;
• a first current source configured to set a current in the replica transistor, wherein an output current of the FA is set to a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio;
• a second current source coupled to a source or drain region of the replica transistor, and
• a register circuit, wherein a register value stored in the register circuit sets the clamped output current value;
• and
• a control circuit configured to activate the switch circuit and change the register value to change current of the second current source and a gate-to-source voltage of the replica transistor to change the clamped output current value of output current of the FA.

An amplifier comprising:

• an output circuit stage having an output transistor;
• and
• an adjustable current clamp circuit coupled to the output transistor, wherein the adjustable current clamp circuit includes:
• a replica transistor coupled as a current mirror pair to the output transistor of the output circuit stage, wherein the replica transistor is a field effect transistor (FET) and is scaled in size to the output transistor by a size ratio;
• a first current source configured to set a current in the replica transistor, wherein an output current of the amplifier is set to a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio;
• a second current source coupled to a source or drain region of the replica transistor, and
• a register circuit, wherein a register value stored in the register circuit sets current of the second current source to set a gate-to-source voltage of the replica transistor to set the clamped output current value.