Latch, processor including latch, and computing apparatus

A latch with an inverted output, comprising:

• an input stage configured to receive a latch input;
• an output stage configured to output a latch output;
• an intermediate node disposed between an output of the input stage and an input of the output stage, wherein a potential at the intermediate node is floating during a part of time of operation, and wherein the output stage is configured to receive a signal at the intermediate node as an input;
• and
• a feedback stage configured to receive the latch output and provide a feedback to the intermediate node,
• wherein the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state,
• wherein the latch output is inverted from the latch input,
• wherein in the latch, the potential at the intermediate node is capable of being maintained, the latch is configured to not use a high-threshold transistor as a transistor as a transistor connected to the intermediate node, and the latch is configured such that a threshold of the transistor connected to the intermediate node in the latch is substantially the same as those of other transistors in the latch, and
• wherein the latch is configured to work at a first frequency in an operation state, and work at a second frequency lower than the first frequency in a sleep or idle state without malfunction, the second frequency is configured such that a dynamic latch obtained by removing the feedback stage from the latch incurs malfunction at the second frequency.