Clock distribution device, and signal processing device and image display apparatus including same
AssigneeLG Electronics Inc.
InventorsMikko Lapinlahti, Klaus Jokinen
Life of this patent
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Abstract
The present disclosure relates to a clock distribution device, and a signal processing device and an image display apparatus including the same. The clock distribution device according to an embodiment of the present disclosure includes: a latch configured to receive a first pulse signal among the first pulse signal and a second pulse signal having non-overlapping high levels; and a flip-flop configured to receive an inverted signal in which the second pulse signal is inverted, wherein an output clock signal is output based on an output signal of the latch, an input clock signal, and an output signal of the flip-flop. Accordingly, the input clock signal may be simply distributed.
Claims18
A clock distribution device comprising:
- a latch configured to receive a first pulse signal among the first pulse signal and a second pulse signal having non-overlapping high levels;
- a flip-flop configured to receive an inverted signal in which the second pulse signal is inverted;
- a first NAND gate configured to operate based on receiving an output signal of the latch and an input clock signal;
- an OR gate configured to operate based on receiving an output signal of the flip-flop and the input clock signal;
- and
- a second NAND gate configured to operate based on receiving an output signal of the first NAND gate and an output signal of the OR gate,
- wherein the second NAND gate outputs an output clock signal, and
- wherein the output clock signal is output based on the output signal of the latch, the input clock signal, and the output signal of the flip-flop.
A clock distribution device comprising:
- a latch configured to receive a first pulse signal among the first pulse signal and a second pulse signal having non-overlapping high levels;
- an inverter configured to invert the second pulse signal;
- a flip-flop configured to receive an output signal of the inverter;
- a first NAND gate configured to operate based on receiving an output signal of the latch and an input clock signal;
- an OR gate configured to operate based on receiving an output signal of the flip-flop and the input clock signal;
- and
- a second NAND gate configured to operate based on receiving an output signal of the first NAND gate and an output signal of the OR gate, and output an output clock signal.
An image display apparatus comprising:
- a display;
- and
- a signal processing device including a clock distribution device,
- wherein the clock distribution device comprises:
- a latch configured to receive a first pulse signal among the first pulse signal and a second pulse signal having non-overlapping high levels;
- a flip-flop configured to receive an inverted signal in which the second pulse signal is inverted;
- a first NAND gate configured to operate based on receiving an output signal of the latch and an input clock signal;
- an OR gate configured to operate based on receiving an output signal of the flip-flop and the input clock signal;
- and
- a second NAND gate configured to operate based on receiving an output signal of the first NAND gate and an output signal of the OR gate,
- wherein the second NAND gate outputs an output clock signal, and
- wherein the output clock signal is output based on the output signal of the latch, the input clock signal, and the output signal of the flip-flop.
Dependencies are inferred from the claim text.