Clocking scheme for reduced noise in continuous-time sigma-delta adcs preliminary class
AssigneeInvenSense, Inc.
InventorsOmid Oliaei, Aurelio Pellegrini, Daniele Ottini
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Abstract
A circuit for a feedback system incorporates a gating mechanism to reduce flicker noise (e.g., a source for bias instability within a MEMS device) at a digital output. The gating mechanism generates a gating pulse with a delay period (e.g., a common, or fixed, delay including symmetrical rising and falling edge delays) that overrides internal delays (e.g., asymmetrical rising and falling edge delays) of a phase generator to prevent propagation delay (e.g., delay affected by jitter) from reaching subsequent feedback components (e.g., a digital-to-analog converter (DAC)) and contributing to the generation of flicker noise within the system.
Claims20
A circuit for reducing flicker noise in a sensor signal path, comprising:
- a comparison block coupled to receive a first signal within the sensor signal path and to change an output state of a comparison block output signal based on whether the first signal is transitioning between a first value and a second value;
- a gating pulse generator coupled to receive the comparison block output signal, wherein a gating pulse having a delay period is output from the gating pulse generator when the output state of the comparison block output signal changes;
- and
- a gating stage, wherein a second signal is an inverted version of the first signal, wherein the gating stage receives the gating pulse, a third signal that is based on the first signal, and a fourth signal that is based on the second signal, and wherein a transition of the third signal from a third value to a fourth value and a transition of the fourth signal from a fifth value to a sixth value are delayed based on the delay period of the gating pulse.
A method for reducing delay mismatch owing to jitter, comprising:
- receiving, from a phase generator, a signal and an inverted signal, wherein transitions of the signal and the inverted signal are misaligned based on respective delays affected by jitter;
- and
- overriding the transitions of the signal and the inverted signal to eliminate the delay mismatch between the respective delays.
Dependencies are inferred from the claim text.