Integrated circuit and method of forming the same

A flip-flop comprising:

• a first input circuit coupled to a first node, and being configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal inverted from the first clock signal;
• a first NOR logic gate coupled between the first node and a second node, and being configured to generate a second signal responsive to the first signal and a first reset signal;
• a first stacked gate circuit coupled between the first node and a third node, the first stacked gate circuit being configured to generate a third signal responsive to at least the first signal;
• a first NAND logic gate coupled between the third node and a fourth node, and being configured to generate a fourth signal responsive to the third signal and a second reset signal inverted from the first reset signal;
• and
• a first output circuit coupled to the fourth node, and being configured to generate a first output signal responsive to the fourth signal,
• a first reset buffer circuit coupled to the first NAND logic gate, the first reset buffer circuit being configured to generate a first inverted reset signal responsive to the first reset signal;
• and
• a first reverse stacked gate circuit coupled between the first node and the second node, the first reverse stacked gate circuit being configured to set the first signal responsive to the second signal.

A flip-flop comprising:

• a first input circuit coupled to a first node, and being configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal inverted from the first clock signal;
• a first NOR logic gate coupled between the first node and a second node, and being configured to generate a second signal responsive to the first signal and a first reset signal;
• a first stacked gate circuit coupled between the first node and a third node, the first stacked gate circuit being configured to generate a third signal responsive to at least the first signal;
• a first NAND logic gate coupled between the third node and a fourth node, and being configured to generate a fourth signal responsive to the third signal and a second reset signal inverted from the first reset signal;
• a first output circuit coupled to the fourth node, and being configured to generate a first output signal responsive to the fourth signal;
• a first reverse stacked gate circuit coupled between the first node and the second node, the first reverse stacked gate circuit being configured to set the first signal responsive to the second signal;
• and
• a second reverse stacked gate circuit coupled between the third node and the fourth node, the second reverse stacked gate circuit being configured to set the third signal responsive to the fourth signal.